1. Field of the Invention
The invention relates to a tester such as an IC tester for testing an IC Integrated Circuit), more particularly to a pattern data transfer circuit installed inside the tester for transferring pattern data.
2. Prior Art
Integrated circuits have been recently rapidly employed in various electric equipment. Products such as an IC, an LSI (large Integrated Circuit) are realized by circuits having functions of various elements such as a resistor, a capacitor, a transistor which are formed by printing, evaporating process, and the like. However, there occur slight variations in characteristics among various mass-produced devices. Under the circumstances, a test is performed whether characteristics of an IC, an LSI is up to a given standard or not using an IC tester.
Hereupon, a conventional pattern data transfer circuit used inside an IC tester is now described hereinafter.
FIG. 4 is a block diagram showing a conventional pattern data transfer circuit and an associated circuit connected to this pattern data transfer circuit 1. As shown in FIG. 4, the pattern data transfer circuit 1 comprises a CPU (Central Processing Unit) 2, a plurality of pattern memories 3 and a plurality of pattern generating circuits 4. The pattern data transfer circuit 1 is connected to a plurality of waveform shaping circuits 5 and a plurality of pin electronics 6 for testing the operation of a DUT (Device Under Test) 7. The pattern data transfer circuit 1 is also connected to a memory 8 and a RAM (Random Access Memory) 9, described later.
The pattern memories 3, the pattern generating circuits 4, the waveform shaping circuits 5 and the pin electronics 6 are respectively provided by the number corresponding to the number of tester channels of the IC tester built in the pattern data transfer circuit 1.
The detail of each component is now described. The DUT 7 is formed of an IC, an LSI, etc. and it is the object to be measured when the IC tester checks the operation of the DUT 7. Respective input/output pins of the DUT 7 are connected to the pin electronics 6 which are provided every tester channels. The memory 8 stores in advance therein various device programs corresponding to the variety of DUTs 7. The CPU 2 reads out device programs corresponding to the specified DUT 7 from the memory 8 and stores it in the RAM 9, thereby controlling hardware components inside the IC tester in accordance with the device programs. The CPU 2 temporarily stores adapter board data, pattern data respectively read out from the memory 8 in CPU memories 2a, 2b built therein. The function of the CPU 2 except that set forth above is described later.
Next, the adapter board and the pattern data are described These data are used by the device programs. FIG. 5 shows an example of the adapter board data. The adapter board data are used for specifying tester channels connected to respective input/output pins of the DUT 7 and comprise a plurality of groups composed of respective data of ┌Pin Group┘, ┌Pin Name┘, and ┌Tester Channel┘. The ┌Pin Group┘ is used for dividing the input/output pins of the DUT 7 into those for every attribute and composed of those of xe2x80x9cDATAxe2x80x9d, xe2x80x9cADDRESSxe2x80x9d, xe2x80x9cMODExe2x80x9d, xe2x80x9cCLOCKxe2x80x9d and so forth Exemplified in FIG. 5 is only the pin group of address (xe2x80x9cADDRESSxe2x80x9d in the same figure) and data (xe2x80x9cDATAxe2x80x9d in the same figure). The ┌Pin Name┘ is an inherent name given to distinguish the respective input/output pins of the DUT 7 from one another. The ┌Tester Channel┘ is data which are assigned to the pin electronics 6 connected to the respective input/output pins of the DUT 7 for distinguishing the tester channels.
The first adapter board data shown in FIG. 5 relates to a pin having xe2x80x9cADDRESSxe2x80x9d included in ┌Pin Group┘ and xe2x80x9cA0xe2x80x9d given to ┌Pin Name┘ which corresponds to tester channel xe2x80x9c1xe2x80x9d as ┌Tester Channel┘. Likewise, any pin having xe2x80x9cA1xe2x80x9d to xe2x80x9cA7xe2x80x9d as ┌Pin Name┘ has xe2x80x9cADDRESSxe2x80x9d included in ┌Pin Group┘ and each pin corresponds to tester channels xe2x80x9c4xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c15xe2x80x9d, xe2x80x9c31xe2x80x9d, xe2x80x9c40xe2x80x9d, xe2x80x9c60xe2x80x9d, and xe2x80x9c61xe2x80x9d as the ┌Tester Channel┘. A pin having xe2x80x9cDATAxe2x80x9d belonging to ┌Pin Group┘ and xe2x80x9cD0xe2x80x9d given to ┌Pin Name┘ corresponds to a tester channel xe2x80x9c80xe2x80x9d as ┌Tester Channel┘. The data following the above data are not illustrated, but they likewise correspond to tester channels as set forth above.
FIG. 6 shows an example of pattern data corresponding to the adapter board data shown in FIG. 5. Each pattern data is represented by 3-bit data of xe2x80x9cHiLOxe2x80x9d, xe2x80x9cI/Oxe2x80x9d, and xe2x80x9cStrobe Maskxe2x80x9d. Respective pattern data are used for controlling output levels of a driver waveform to be inputted to the pins of the DUT 7 (xe2x80x9cHiLoxe2x80x9d in the same figure) by way of tester channels corresponding to the respective ┌Pin Name┘, presence or absence of the receiving of the waveform outputted from the DUT 7 (xe2x80x9cI/Oxe2x80x9d in the same figure), and presence or absence of decision of High/Low (xe2x80x9cStrobe Maskxe2x80x9d in the same figure) relative to the received waveform. Values of respective data contained in the pattern data mean as follows.
For example, pattern data such as xe2x80x9c0 outputxe2x80x9d, xe2x80x9c1 outputxe2x80x9d, xe2x80x9cL expectationxe2x80x9d, xe2x80x9c1 outputxe2x80x9d, xe2x80x9c1 outputxe2x80x9d, and xe2x80x9cH expectationxe2x80x9d, . . . , . . . , are given to ┌Tester Channel┘ xe2x80x9c1xe2x80x9d corresponding to ┌Pin Name┘ xe2x80x9cA0xe2x80x9d.
As evident from FIG. 6, for the xe2x80x9cI/Oxe2x80x9d data and xe2x80x9cStrobe Maskxe2x80x9d data of the tester channel belonging to the Pin Group xe2x80x9cADDRESSxe2x80x9d, the same data are to be used for all the tester channels in the direction of a time axis. The pin group having the pattern common to all tester channels in respective pin groups is sometimes called hereinafter xe2x80x9ccommon pin groupxe2x80x9d.
Pattern data for every tester channels shown in FIG. 6 are stored in the pattern memories 3 shown in FIG. 4. The pattern generating circuits 4 generate pattern data (see xe2x80x9cPATTERN DATAxe2x80x9d shown in FIG. 6) on the basis of data stored in the pattern memories 3 corresponding to the their own tester channels and output the pattern data to the waveform shaping circuits 5 corresponding to the tester channels. The waveform shaping circuits 5 shape the driver waveform necessary for testing the DUT 7 in response to pattern data outputted from the pattern generating circuits 4 and output the shaped driver waveforms to the pin electronics 6 corresponding to the tester channels.
The pin electronics 6 are circuits at the side of the ICs used as interfaces between respective input/output pins of the DUT 7 and connected to the respective input/output pins of the DUT 7. The pin electronics 6 output the driver waveforms outputted from the waveform shaping circuits 5 to the respective input pins of the DUT 7 and receive waveforms outputted from the respective output pins of the DUT 7.
Described next along a flow chart in FIG. 7 is pattern data transfer operation by the pattern data transfer circuit 1. Described hereinafter is a case of transfer of pattern data (FIG. 6) corresponding to respective pins having xe2x80x9cA0xe2x80x9d to xe2x80x9cA7xe2x80x9d as ┌Pin Name┘ among the adapter board data (FIG. 5).
First, the CPU 2 reads out a device program corresponding to the DUT 7 from the memory 8 and transfers it to the RAM 9, and it transfers the adapter board data and pattern data used by the device program to the CPU memories 2a, 2b in which these data are temporarily stored.
Next, the CPU 2 recognizes ┌Tester Channel┘ corresponding to xe2x80x9cA0xe2x80x9d of ┌Pin Name┘ as xe2x80x9c1xe2x80x9d referring to the adapter board data in the CPU memory 2a of the CPU 2, and selects the tester channel xe2x80x9c1xe2x80x9d (Step 11). Then, the CPU 2 extracts xe2x80x9cHiLoxe2x80x9d data corresponding to ┌Pin Name┘ xe2x80x9cA0xe2x80x9d referring to pattern data in the CPU memory 2b of the CPU 2 (Step 12), and transfers the extracted xe2x80x9cHiLoxe2x80x9d data to the pattern memory 3 corresponding to the tester channel xe2x80x9c1xe2x80x9d (step S13). Subsequently similarly, the CPU 2 extracts xe2x80x9cI/Oxe2x80x9d data corresponding to the tester channel xe2x80x9c1xe2x80x9d from the pattern data (step S14), and it transfers the extracted xe2x80x9cI/Oxe2x80x9d data to the pattern memory 3 corresponding to the tester channel xe2x80x9c1xe2x80x9d (step S15), thereafter it extracts xe2x80x9cStrobe Maskxe2x80x9d data corresponding to the tester channel xe2x80x9c1xe2x80x9d from the pattern data (step S16), and transfers the extracted xe2x80x9cStrobe Maskxe2x80x9d data to the pattern memory 3 corresponding to the tester channel xe2x80x9c1xe2x80x9d.
Subsequently, the CPU 2 decides whether there is any input/output pin to which data is not transferred (step S18). Since there remains a processing relating the input/output pins for ┌Pin Name┘ xe2x80x9cA1xe2x80x9d to xe2x80x9cA7xe2x80x9d (result of decision is xe2x80x9cYxe2x80x9d), the CPU 2 returns its processing to step S11 where a transfer operation of the pattern data is executed like the case of ┌Pin Name┘ xe2x80x9cAOxe2x80x9d. Consequently, a series of specified pattern data transfer operation is completed if the pattern data transfer processing relating to the ┌Pin Name┘ xe2x80x9cA7xe2x80x9d is completed (result of decision is xe2x80x9cNxe2x80x9d).
As mentioned above, in the conventional pattern data transfer circuit 1, reading operation of xe2x80x9cHiLoxe2x80x9d data, xe2x80x9cI/Oxe2x80x9d data, xe2x80x9cStrobe Maskxe2x80x9d data and transfer operation of these data to the pattern memories 3 are respectively sequentially performed for every selected tester channels. Accordingly, there arises the drawback that the number of data transfer becomes large, which results in the long transfer time as a whole.
The invention has been made in view of the problems of the conventional pattern data transfer circuit, and it is an object of the invention to provide a pattern data transfer circuit capable of parallelly executing the pattern transfer processings for every tester pattern channels as much as possible, so that the number of data transfer is reduced, thereby shortening the time for transferring data.
To achieve the above objects, the pattern data transfer circuit according to a first aspect of the invention comprises tester channels and pattern data for measurement assigned to respective pins of a device under test which are divided into pin groups for every attribute, common pin groups having a common pattern in which all pattern data of all pins in the pin group are common pattern memories provided every tester channels to which respective pattern data corresponding to respective tester channels are transferred, the pattern data transfer circuit is characterized in further comprising pin group data generating means for generating pin group data representing all the tester channels assigned to respective pins in the common pin groups on the basis of the assignment of the respective tester channels relative to the pins, and transfer means for extracting the common patterns among the pattern data assigned to the common pin group, and parallelly and simultaneously transferring the extracted common patterns to all pattern memories corresponding to the respective tester channels represented by the pin group data.
In the pattern data transfer circuit according to a second aspect of the invention, the pattern memories are independently and selectively formed in response to a selection signal and the transfer means supplies the common patterns to all the pattern memories and also supplies the selection signals to the pattern memories corresponding to the tester channels represented by the pin group data.